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dma_channel_hw_t | ch [16] |
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union { | |
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struct { | |
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io_rw_32 intr | |
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io_rw_32 inte0 | |
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io_rw_32 intf0 | |
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io_rw_32 ints0 | |
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uint32_t __pad0 | |
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io_rw_32 inte1 | |
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io_rw_32 intf1 | |
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io_rw_32 ints1 | |
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uint32_t __pad1 | |
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io_rw_32 inte2 | |
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io_rw_32 intf2 | |
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io_rw_32 ints2 | |
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uint32_t __pad2 | |
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io_rw_32 inte3 | |
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io_rw_32 intf3 | |
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io_rw_32 ints3 | |
| } | |
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dma_irq_ctrl_hw_t irq_ctrl [4] | |
| }; | |
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io_rw_32 | timer [4] |
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io_wo_32 | multi_channel_trigger |
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io_rw_32 | sniff_ctrl |
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io_rw_32 | sniff_data |
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uint32_t | _pad0 |
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io_ro_32 | fifo_levels |
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io_wo_32 | abort |
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io_ro_32 | n_channels |
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uint32_t | _pad1 [5] |
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io_rw_32 | seccfg_ch [16] |
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io_rw_32 | seccfg_irq [4] |
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io_rw_32 | seccfg_misc |
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uint32_t | _pad2 [11] |
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io_rw_32 | mpu_ctrl |
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dma_mpu_region_hw_t | mpu_region [8] |
The documentation for this struct was generated from the following file:
- include/hardware/structs/dma.h