#include "pico.h"
#include "hardware/regs/rvcsr.h"
Go to the source code of this file.
|
| #define | _riscv_read_csr(csrname) |
| #define | _riscv_write_csr(csrname, data) |
| #define | _riscv_set_csr(csrname, data) |
| #define | _riscv_clear_csr(csrname, data) |
| #define | _riscv_read_write_csr(csrname, data) |
| #define | _riscv_read_set_csr(csrname, data) |
| #define | _riscv_read_clear_csr(csrname, data) |
| #define | riscv_read_csr(csrname) |
| #define | riscv_write_csr(csrname, data) |
| #define | riscv_set_csr(csrname, data) |
| #define | riscv_clear_csr(csrname, data) |
| #define | riscv_read_write_csr(csrname, data) |
| #define | riscv_read_set_csr(csrname, data) |
| #define | riscv_read_clear_csr(csrname, data) |
|
|
static uint32_t | riscv_encode_imm_u (uint32_t x) |
|
static uint32_t | riscv_encode_imm_i (uint32_t x) |
|
static uint32_t | riscv_encode_imm_u_hi (uint32_t x) |
|
static uint32_t | riscv_encode_imm_b (uint32_t x) |
|
static uint32_t | riscv_encode_imm_s (uint32_t x) |
|
static uint32_t | riscv_encode_imm_j (uint32_t x) |
|
static uint16_t | riscv_encode_imm_cj (uint32_t x) |
|
static uint16_t | riscv_encode_imm_cb (uint32_t x) |
|
static uint16_t | riscv_encode_imm_ci (uint32_t x) |
◆ _riscv_clear_csr
| #define _riscv_clear_csr |
( |
| csrname, |
|
|
| data ) |
Value: ({ \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrci " #csrname ", %0" : : "i" (data)); \
} else { \
asm volatile ("csrc " #csrname ", %0" : : "r" (data)); \
} \
})
◆ _riscv_read_clear_csr
| #define _riscv_read_clear_csr |
( |
| csrname, |
|
|
| data ) |
Value: ({ \
uint32_t __csr_tmp_u32; \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrrci %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \
} else { \
asm volatile ("csrrc %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \
} \
__csr_tmp_u32; \
})
◆ _riscv_read_csr
| #define _riscv_read_csr |
( |
| csrname | ) |
|
Value: ({ \
uint32_t __csr_tmp_u32; \
asm volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \
__csr_tmp_u32; \
})
◆ _riscv_read_set_csr
| #define _riscv_read_set_csr |
( |
| csrname, |
|
|
| data ) |
Value: ({ \
uint32_t __csr_tmp_u32; \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrrsi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \
} else { \
asm volatile ("csrrs %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \
} \
__csr_tmp_u32; \
})
◆ _riscv_read_write_csr
| #define _riscv_read_write_csr |
( |
| csrname, |
|
|
| data ) |
Value: ({ \
uint32_t __csr_tmp_u32; \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrrwi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \
} else { \
asm volatile ("csrrw %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \
} \
__csr_tmp_u32; \
})
◆ _riscv_set_csr
| #define _riscv_set_csr |
( |
| csrname, |
|
|
| data ) |
Value: ({ \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrsi " #csrname ", %0" : : "i" (data)); \
} else { \
asm volatile ("csrs " #csrname ", %0" : : "r" (data)); \
} \
})
◆ _riscv_write_csr
| #define _riscv_write_csr |
( |
| csrname, |
|
|
| data ) |
Value: ({ \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrwi " #csrname ", %0" : : "i" (data)); \
} else { \
asm volatile ("csrw " #csrname ", %0" : : "r" (data)); \
} \
})
◆ riscv_clear_csr
| #define riscv_clear_csr |
( |
| csrname, |
|
|
| data ) |
Value:_riscv_clear_csr(csrname, data)
◆ riscv_read_clear_csr
| #define riscv_read_clear_csr |
( |
| csrname, |
|
|
| data ) |
Value:_riscv_read_clear_csr(csrname, data)
◆ riscv_read_csr
| #define riscv_read_csr |
( |
| csrname | ) |
|
◆ riscv_read_set_csr
| #define riscv_read_set_csr |
( |
| csrname, |
|
|
| data ) |
Value:_riscv_read_set_csr(csrname, data)
◆ riscv_read_write_csr
| #define riscv_read_write_csr |
( |
| csrname, |
|
|
| data ) |
Value:_riscv_read_write_csr(csrname, data)
◆ riscv_set_csr
| #define riscv_set_csr |
( |
| csrname, |
|
|
| data ) |
Value:_riscv_set_csr(csrname, data)
◆ riscv_write_csr
| #define riscv_write_csr |
( |
| csrname, |
|
|
| data ) |
Value:_riscv_write_csr(csrname, data)